Processes for fabricating integrated circuit devices typically include the formation of a relatively large array of integrated circuits that are replicated at side-by-side locations on an integrated circuit wafer. These fabricating processes also typically include the formation of multiple levels of electrically insulating layers that extend across the entire surface of a wafer and are selectively and individually patterned using conventional photolithography techniques. During photolithography, an organic material layer, such as a photo-resist (PR) mask layer, may be deposited on an electrically insulating layer and then patterned to define a mask. This mask may contain a pattern that is replicated for each of the integrated circuits to be formed adjacent an interior of the semiconductor wafer and adjacent an edge (i.e., periphery) of the semiconductor wafer. Unfortunately, the steps to pattern the mask layer into a mask may result in mask patterns having non-uniform lateral dimensions that vary according to location on the semiconductor wafer. For example, it is not uncommon for a mask pattern that defines a critical dimension (CD) of a structure within in an integrated circuit extending adjacent the edge of the semiconductor wafer to be narrower than the corresponding mask pattern extending adjacent an interior of the semiconductor wafer (i.e., near the center of the wafer). This nonuniformity in the mask pattern dimensions, which frequently results from the non-uniform etching characteristics associated with wafer-scale etching processes, can lead to complications in wafer level processing and result in poor device yield and reliability.